b0VIM 7.4Y\T4 rubenworkstation~ruben/docs/grad/arch/memory_notes.txtutf-8 3210#"! Utppnyr$adpfUSBj% ^ E D  } M J 5 #   a F  [ K  l O 8 V:xF*l8#W/.c/Z)  m mem 6.41 Locality of reference: The theory that areas of further off the system core. processor and less expensive and larger memory resources are 6.4 Memory Heirachy: Traditional memo 6.4 Memory Heirachy: Traditional memory design where the memory. the bits and words are translated in physical is essential to its use and description. How 6.354 Organization Design - Especially for RAM 6.353 Nonerasable: ROM in Semiconductor Material until deliberately changed 6.352 NonVolatile: Memory remains once stored powered down. 6.351 Volatile: Leaks Memory and Disapates when 6.35 Memory Physical Properties: 6.34 Magneto-Optical 6.33 Optical .321 NonVolatile 6.32 Magnetic Surface .311 Volatile or NonVolatile 6.31 Semiconductor 6.3 Physical Memory Types: transfer in and out of a memory unit .223 Transfer Rate: The rate in which data can .2221 Most a Random Access Memory Issue completes. time where the a R/W can start after one .222 Memory Cycle Time: System Bus dependent an individual R/W .221 Access Time: The Time it takes to perform 6.22 Performance 6.21 Capacity 6.2 Memory Charactoristics: .156 Examples: Some Cache memories has its own addressing location .155 Retrieval Time contastant - Each location rather than its address. .154 A word is retrieved based on its content, .153 Does this for all Words simulatenously locations within a word for a specified match .152 enables one to make a comparison of desired bit .151 A type of random access 6.15 Associative Access: .143 Example: Main Memory and certain cache. constant of previous memory access and access is fairly .142 Time to access each location is independent .141 Each Memory Unit has a specific, unique, wired address 6.14 Random Access: .135 Example: Disk Units .134 Variable Access Time location then sequential counting to find the exact data .133 Direct Acces to the area of the storage and based on physical location .132 Block or Records have unique Addresses sequntial) .131 Shared Access (R/W) mechanism (similar to 6.13 Direct Access: .126 Example: Backup Tapes find what you want to use for R/W .125 Access requires moving through records to .124 Shared Read/Write Mechanism is used Record Accessing easier .123 Addressing Information is stored to make .122 Access is linear .121 Memory organzed into Record Units 6.12 Sequenction Access: Associative Random Direct Sequential 6.11 Methods: 6.1 Memory Access: 2A = N <==============================What? address and the number of addressable units: 6.041 The relationship between length in bits A of an allow for Byte Size addressing 6.04 Addressable Units: Usually a Word size but some units word, such as a block. 6.034 External: Often transfered in units larger than a memory at a single time. 6.033 Main Memory: The Number of bits read/write into 6.032 May be equal to a word or larger (64, 128, 256) 6.031 Equal to the number of lines in and out of the memory device 6.03 Units of Tranfer: 6.023 Words (8,16,32 and 64 bits) 6.022 Bytes 6.021 Bits 6.02 Capacity: 6.0122 Availble through I/O controllers 6.01212 Tapes and Disks 6.0121 Peripheral Storage Devices 6.012 external 6.0114 Cache 6.0113 Control Unit Memory 6.0112 Registers: Processor Local Memory 6.0111 Main Memory 6.011 internal 6.01 Location:6.0 Computer Memoryady]$# ml_P>2"! q D 8 7 h A   z y R & y U A @ X 5  nN/shgQ5|Y7iE,+rkWC-~\Q>% igfe`[ .5272 Unified or Split .5271 Single or Two Level relationship: 6.527 Number of caches and their 6.526 Line Size .5252 Write Back .5251 Write Through 6.525 Write Policy .5244 Random (LFU) .5243 Least Frequently Used .5242 First in First Out (FIFO) .5241 Least Recently Used (LRU) 6.524 Replacement Algorithm .5233 Se 22 An address is cache line assigned to any block can be 21 Any Memory .5232 Associative - http://www.nylxs.com/docs/grad_school/arch/direct_cache_model.png cache line. address to a single possible .5231 Direct - Maps each memory must be constructed memory locations, an algorithm cache so in order to reach all The Memory is larger than the 6.523 Mapping Function: 6.522 Cache Size memory process running the virtual address to specify the virtual bits need to be added to the application switches or extra flushed clean between and therefor, the cache must be 521122: Addresses not unique hits (good) 521121: No MMU access for cache between the and the MMU Addressing: Cache is 6.52112 Logical bus. cache and the system the processor or between sit between cache and Management Unit: Can 6.52111 MMU - Memory address. addresses for real physical Module translates virtual Hardware Memory Management 6.5211 Virtual Memory - 6.521 Addressing: Logical or Physical 6.52 Elements of Cache Design: bus. system bus, preventing traffic on the processor, turns off access to the between the system bus and the the cache, which has the control line cache in a parallel architecture, then When a memory address is listed in the .512131 Parallel Control http://www.nylxs.com/docs/grad_school/arch/cache_memory_parellel.png simultaneously. the cache and the CPU registers can call for the memory and it enters when you have a cache miss, the cache parallel. This gives the advantage that CPU to the Main Memory and the Cache in Address lines can be connected from the .51213 Alternatively, the Data and send the data on to the CPU block with the address. The cache then the blocks in the cache, retrieve the .51212 If that address is not in any of return the data for the address .5121 If it is in the cache block, contained in the cache. 6.512 Check if the address is in the block 6.511 Processor generates a read address words at a single location. 6.51 Each Cache location would have a numer of memory Fast Fastest Fast Less Slow CPU <==> L1 <==> L2 <==> L3 <==> Main Memory fast slow CPU <====> Cache <====> Main Memory 6.5 Memory Caching Technique Tape Magnetic Disk Main Memory Cache Register ----------- Heirarchy 6.441 BAckup Tapes 6.44 Offline Storage: 6.431 Magnetic Disk, Optical Disks, etc 6.43 Outboard Storage: 6.421 Registers, Cache, Main Memory 6.42 Inboard Memory: system cashes clusters of memory for processing usage. advantage to a system of memory movement where the used than outside clusters of memory. This gives memory, over the short period of time, is more intenslyad0ih0 6.41 Locality of reference: The theory that areas of further off the system core. processor and less expensive and larger memory resources are fastest and most expensive form of memory is close to theadP $qW;$#kE  Y G '     .5272 Unified or Split .5271 Single or Two Level relationship: 6.527 Number of caches and their 6.526 Line Size .5252 Write Back .5251 Write Through 6.525 Write Policy .5244 Random (LFU) .5243 Least Frequently Used .5242 First in First Out (FIFO) .5241 Least Recently Used (LRU) 6.524 Replacement Algorithm .5234 Set Associative to reduce their disadvantages. each of the above in an effort .5233 Set Associative - A little bit of the cache or not determine if it is in address in order to the currently requested memory for a matching tag as 23 Every line is looked WORD field interpreted as a TAG or